1. Field of the Invention
The present invention generally relates to semiconductor fabrication. More specifically, the present invention relates to systems and methods pertaining to wafer stacks that involve dicing the wafer stacks in order to provide access to interior structures and/or components of the wafer stacks.
2. Description of the Related Art
Several semi-conductor device fabrication techniques involve the use of multiple semi-conductor wafers that are bonded to each other to form a wafer stack. In one such technique, for example, components and/or circuitry (“processing”) is provided on the upper surface of a first wafer and on the upper surface of a second wafer. The first wafer is then inverted and aligned with the second wafer so that corresponding processing of the wafers are aligned with each other. The wafers are engaged with each other and bonded together so that the corresponding processing properly engage each other. For example, the engaged processing may electrically communicate and/or mechanically engage each other. FIGS. 1 and 2 schematically depict this technique.
In FIG. 1, representative portions of a first wafer 102 and a second wafer 104 are depicted. Wafer 102 is configured to provide multiple dies, e.g., die 106 and die 108. Likewise, wafer 104 is configured to provide multiple dies, e.g., die 110 and die 112. Each die can incorporate one or more features and/or components that are configured to engage one or more corresponding features and/or components of a die of the other wafer. For example, component 116 is configured to engage component 118, component 120 is configured to engage component 122, component 124 is configured to engage component 126, and component 128 is configured to engage component 130. Also depicted in FIG. 1 are pads 132 and 134, which are provided so as to facilitate communication of signals on and off of the wafers. In order to facilitate communication of signals using the pads, vias 136 and 138 are provided in wafer 102.
In FIG. 2, wafers 102 and 104 are shown bonded together to form a wafer stack 200. Wafers 102 and 104 typically are bonded together by a conventional technique, such as thermal compression, eutectic, and/or anodic bonding. As shown in FIG. 2, once the wafers are bonded together, the processing of the wafers generally are disposed between substrates 202 and 204 of the wafers. Note that via 138 is aligned with pad 132, and via 136 is aligned with pad 134.
In order to separate die assemblies from the wafer stack, various through-cuts typically are made through the stack. As used herein, a “through-cut” refers to dicing of a portion of the wafer stack so as to separate the wafer stack at the dicing location. A representative through-cut TY2 is depicted in FIG. 3. Also depicted in FIG. 3 are various other cut locations that are designated for receiving through-cuts. These locations are designated TY1, TX1, and TX2. As is known, a through-cut is a cut made through the material of the stack that enables the stack to be separated at the cut location. Thus, through-cut TY2 may be cut through the stack from one side to the other side or may be cut through a sufficient depth of the material so that the stack can be separated, such as by fracturing the material remaining at the cut location.
By dicing a wafer stack in the manner depicted in FIG. 3, separate die assemblies, such as die assemblies 402 and 404 (FIG. 4) can be provided. Also depicted in FIG. 4 is a typical configuration for providing signals on and/or off the die assembly. More specifically, a transmission medium (represented by an arrow) can be arranged through the via so that communication, e.g., electrical communication, optical communication, etc., may be facilitated between a pad of the die assembly and components external to the die assembly. However, due to design, manufacturing, performance, and/or assembly considerations, among others, providing one or more vias in a wafer stack and/or die assembly may not be desirable. Therefore, there is a need for improved systems and methods that address these and/or other shortcomings of the prior art.